Japanese Patent Application Laid-open Publication No. 2000-503491 (Patent Document 1) describes a power semiconductor device in which a plurality of wires are connected to a plurality of electrode pads on an upper surface of a semiconductor chip. And, the Patent Document 1 also describes a structure in which wires are connected to a plurality of positions in a part of the plurality of electrode pads.
Japanese Patent Application Laid-open Publication No. S61-290747 (Patent Document 2) describes a structure in which a bonding pad is connected to a test pad via a wiring.